Chris Domas is an embedded systems engineer and cyber security researcher, focused on innovative approaches to low level hardware and software RE and exploitation.
There has been a bug in x86 architecture for more than 20 years... just waiting for Chris Domus to escalate privileges.
Chris did the demo on a small, cheap netbook computer. In case it didn't work, he had a stack of netbooks. We saw just running a program where a general user ran a simple program and had root.
Some things are so important that even the hypervisor should not be allowed to execute it.
We originally wanted to do power management without the OS to worry about it - system management mode. SMM becamse a dumping ground for all kinds of things, eventually it took "security" enhancements. Now SMM is imortant: root of turst, TPM emulation and communication, cryptographic authentication...
Whenever there was something important or sensitive or secret, it got stuck in SMM.
Userland is at Ring 3, kernel in Ring 0 . Ring -1 is they hyperviser... Ring -2 is SMM. On modern systems , Ring 0 is not in control. We have to get deeper (and hide from) Ring 0.
If you're in ring 0 and try to read from SMM - you'll just get a bunch of garbage. Memory control separated SMRAM from the rest of the system. If you're in SMM, though, you can read from SMRAM.
There are many protections on SMM - locks, blocks, etc. but most exist in the memory controller hub. Lots of research in this area on how to to get to Ring -2.
The local APIC used to be a physically separate chip that did this management. But, it's more efficient and cheaper to put the local APIC on the CPU. Now it's even faster!
Intel reserved 0xfee0000-0xfee01000 - so to access, you have to do some round about ways to get there. When they created this model, this broke legacy systems that expected that segment of memory to map to something else. Looking at the Intel SDM, c 1997 describes what's happened here in the P6.
Now we're allowed to move where the APIC window is located, allowing us to access APIC reserved space. This "fix" opens systems up to this vulnerability.
If we're in Ring 0, and we try to read SMRAM we will be denied. But, you can do it from SMM. What if we're in Ring 0, and relocate the APIC window. Now, from Ring 0, we can read SMRAM. Now that we can do that, we can modify SMM's view of memory. Now the security enforcer has been removed.
How to attack ring -1 from ring 0? SMRAM acts as a fe haven for SMM code. As long as SMM code stays in SMRAM, ring 0 cannot touch it. But if we can get SMM code to step out of its hiding spot, we can hijack it.
Move APIC over SmRM, corrupt execution , trigger fault in SMM. This gets is to look up an exception handler - under our control. Though, that attack doesn't work. There's an undocumented security feature which causes a triple fault (reset) the system.
He overlayed APIC MMIO range at the SMI entry point: SMBAE+0x80000 - getting the APIC entry point and the SMBAE to overlap.
Now, we just need to store shell code in the APIC registers. The challenge is they have to be 4 K aligned. Place exactly SMI entry. Execution begins @ exactly start of APIC registers.4096 bytes available.
Many registers are largely hardwired to 0, giving few registers that can actually be changed. We need to do something useful before the system resets.
You need to keep things from executing right away before our last byte is activated.
we only really have 4bits to do something to actively attack the system. Looking at the opcode map, not a lot of interesting things.
But, the attack didn't work as expected. We still can't execute from the APIC, so must control the SMM with data alone.
How do we attack code when our only control is to disable some memory?
SMM code comes from system firmware. Intel makes template code, which goes to independent BIOS vendors, then the OEMs (HP, Toshiba, Lenovo) makes more changes.
The only way to make a general attack is to look at the EFI template BIOS code from Intel, as that will be on EVERY system.
From ring 0, we try to sinkhole the DSC to switch it into system management mode. We've lsot control, but maybe it'll let us do something before memroy resets.
(lots of stuff about self rewriting code, and far jumps and long jumps and lots of hex codes)
Then we successfully got the SMM to read code that we could control, by controlling the memory mapping.
With only 8 lines of code, to exploit: hardware remapping, descriptor cache configurations, etc.
In the end, used well behaving code in order to abuse a different area.
This has opened up a new class of exploits. Now that we have Ring -2 control, what can we do? We can disable the cryptographic checks, or turn off temperagur control, brick the system, or install a root kit.
Once we have the control, we can preempt the hypervisor, periodic interception, filter ring 0 i/o, modify memory, escalate processes, etc.
Adapted code from Dmytro Oleksiuk.
We can simultaneously take over all security controls. Mitigations don't look good. This is unpatchable, would need new processors.... Which Intel did. Their developers seem to have found this independently. This is now fixed with Sandy Bridge and Atom 2013. Now check in SMRRs with APIC is relocated.
intel.com/security has a write up on this. They have been easy to work with, and have been working on mitigations where ever it was architecturally possible.
Oracle Solaris 11.3 SRU 29 Released - We've just released Oracle Solaris 11.3 SRU 29. It contains some important security fixes and enhancements. SRU29 is now available from My Oracle Support...